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MMDF2P02E Power MOSFET 2 Amps, 25 Volts
P-Channel SO-8, Dual
These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the drain-to-source diode has a low reverse recovery time. MiniMOSt devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dc-dc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients.
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2 AMPERES, 25 VOLTS RDS(on) = 250 mW
P-Channel D
G S
* * * * * * * * *
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive - Can Be Driven by Logic ICs Miniature SO-8 Surface Mount Package - Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, with Soft Recovery IDSS Specified at Elevated Temperatures Avalanche Energy Specified Mounting Information for SO-8 Package Provided Pb-Free Package is Available
Rating Symbol VDSS VGS ID ID IDM PD Value 25 20 2.5 1.7 13 2.0 16 -55 to 150 245 Unit Vdc Vdc Adc Apk W mW/C C mJ
MARKING DIAGRAM
8 8 1 SO-8, Dual CASE 751 STYLE 11 1 F2P02 = Specific Device Code A = Assembly Location Y = Year WW = Work Week G = Pb-Free Package (Note: Microdot may be in either location) F2PO2 AYWW G G
MAXIMUM RATINGS (TJ = 25C unless otherwise noted) (Note 1)
Drain-to-Source Voltage Gate-to-Source Voltage - Continuous Drain Current - Continuous @ TA = 25C Drain Current - Continuous @ TA = 100C Drain Current - Single Pulse (tp 10 ms) Total Power Dissipation @ TA = 25C (Note 2) Derate above 25C Operating and Storage Temperature Range Single Pulse Drain-to-Source Avalanche Energy - Starting TJ = 25C (VDD = 20 Vdc, VGS = 10 Vdc, Peak IL = 7.0 Apk, L = 10 mH, RG = 25 W) Thermal Resistance, Junction-to-Ambient (Note 2) Maximum Lead Temperature for Soldering Purposes, 0.0625 from case for 10 sec.
PIN ASSIGNMENT
Source-1 Gate-1 Source-2 Gate-2 1 2 3 4 8 7 6 5 Drain-1 Drain-1 Drain-2 Drain-2
TJ, Tstg EAS
Top View C/W C
RqJA TL
62.5 260
ORDERING INFORMATION
Device MMDF2P02ER2 MMDF2P02ER2G Package SO-8 SO-8 (Pb-Free) Shipping 2500 Tape & Reel 2500 Tape & Reel
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Negative sign for P-Channel device omitted for clarity. 2. Mounted on 2 square FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10 sec. max.
(c) Semiconductor Components Industries, LLC, 2006
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: MMDF2P02E/D
1
April, 2006 - Rev. 8
MMDF2P02E
ELECTRICAL CHARACTERISTICS (TA = 25C unless otherwise noted) (Note 3)
Characteristic OFF CHARACTERISTICS Drain-to-Source Breakdown Voltage (VGS = 0 Vdc, ID = 250 mAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 20 Vdc, VGS = 0 Vdc) (VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125C) Gate-Body Leakage Current (VGS = 20 Vdc, VDS = 0) ON CHARACTERISTICS (Note 4) Gate Threshold Voltage (VDS = VGS, ID = 250 mAdc) Temperature Coefficient (Negative) Static Drain-to-Source On-Resistance (VGS = 10 Vdc, ID = 2.0 Adc) (VGS = 4.5 Vdc, ID = 1.0 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS (Note 5) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Gate Charge (VDS = 16 Vdc, ID = 2.0 Adc, VGS = 10 Vdc) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 10 Vdc, RG = 6.0 W) (VDD = 10 Vdc, ID = 2.0 Adc, VGS = 5.0 Vdc, RG = 6.0 W) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCE-DRAIN DIODE CHARACTERISTICS Forward On-Voltage (Note 4) Reverse Recovery Time See Figure 11 (IS = 2.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/ms) Reverse Recovery Storage Charge 3. Negative sign for P-Channel device omitted for clarity. 4. Pulse Test: Pulse Width 300 ms, Duty Cycle 2%. 5. Switching characteristics are independent of operating junction temperature. (IS = 2.0 Adc, VGS = 0 Vdc) VSD trr ta tb QRR - - - - - 1.5 32 19 12 0.035 2.0 64 - - - mC Vdc ns - - - - - - - - - - - - 20 40 53 41 13 29 30 28 10 1.0 3.5 3.0 40 80 106 82 26 58 60 56 15 - - - nC ns (VDS = 16 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss - - - 340 220 75 475 300 150 pF VGS(th) 1.0 - RDS(on) - - gFS 1.0 0.19 0.3 2.8 0.25 0.4 - Mhos 2.0 3.8 3.0 - W Vdc V(BR)DSS 25 - IDSS - - IGSS - - - - 1.0 10 100 nAdc - 2.2 - - Vdc mV/C mAdc Symbol Min Typ Max Unit
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MMDF2P02E
TYPICAL ELECTRICAL CHARACTERISTICS
4 VGS = 10 7 V I D , DRAIN CURRENT (AMPS) 3 4.3 V 2 4.1 V 3.9 V 1 3.7 V 3.5 V 3.3 V 0 0.4 0.8 1.2 1.6 VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS) 2 5V 4.7 V 4.5 V TJ = 25C I D , DRAIN CURRENT (AMPS) 3 100C 2 25C TJ = -55C 1 4
VDS 10 V
0
0 2.5
3 3.5 4 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
4.5
Figure 1. On-Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS) 0.6 0.5 0.4 0.3 0.2 0.1 0 3 4 5 6 7 8 9 10 VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) ID = 1 A TJ = 25C 0.6
Figure 2. Transfer Characteristics
TJ = 25C 0.5
0.4 VGS = 4.5
0.3
0.2 10 V 0.1 0 0.5 1 ID, DRAIN CURRENT (AMPS) 1.5 2
Figure 3. On-Resistance versus Gate-to-Source Voltage
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED) 2.0 VGS = 10 V ID = 2 A 1.5 I DSS , LEAKAGE (nA) 100
Figure 4. On-Resistance versus Drain Current and Gate Voltage
VGS = 0 V
TJ = 125C 10
1.0
0.5
100C
0 -50
-25
0
25
50
75
100
125
150
1
0
4
8
12
16
20
TJ, JUNCTION TEMPERATURE (C)
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On-Resistance Variation with Temperature
Figure 6. Drain-to-Source Leakage Current versus Voltage
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MMDF2P02E
POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (Dt) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because drain-gate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG - VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve.
VDS = 0 V Ciss VGS = 0 V TJ = 25C VGS, GATE-TO-SOURCE VOLTAGE (VOLTS) 1000
During the turn-on and turn-off delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG - VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the off-state condition when calculating td(on) and is read at a voltage corresponding to the on-state when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified.
12 QT 9 VDS 6 Q1 Q2 VGS
16
800 C, CAPACITANCE (pF)
12
600
8
400
Crss
Ciss Coss Crss
200 0 10
3
Q3
4 ID = 2 A TJ = 25C 2 4 6 8 Qg, TOTAL GATE CHARGE (nC) 10 0 12
5 VGS
0 VDS
5
10
15
20
25
30
0
0
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Figure 8. Gate-to-Source and Drain-to-Source Voltage versus Total Charge
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VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
MMDF2P02E
100 VDD = 10 V ID = 2 A VGS = 10 V TJ = 25C t, TIME (ns) 2 TJ = 25C VGS = 0 V IS, SOURCE CURRENT (AMPS) 1.6
1.2
td(off) tr tf td(on) 10 1 10 RG, GATE RESISTANCE (OHMS) 100
0.8
0.4
0 0.6
0.8 1 1.2 1.4 VSD, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
1.6
Figure 9. Resistive Switching Time Variation versus Gate Resistance
Figure 10. Diode Forward Voltage versus Current
di/dt = 300 A/ms I S , SOURCE CURRENT
Standard Cell Density trr High Cell Density trr tb ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA The Forward Biased Safe Operating Area curves define the maximum simultaneous drain-to-source voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance - General Data and Its Use." Switching between the off-state and the on-state may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 ms. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) - TC)/(RqJC). A power MOSFET designated E-FET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases non-linearly with an increase of peak current in avalanche and peak junction temperature. Although many E-FETs can withstand the stress of drain-to-source avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 13). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
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MMDF2P02E
100 I D , DRAIN CURRENT (AMPS) VGS = 20 V SINGLE PULSE TC = 25C
Mounted on 2 sq. FR4 board (1 sq. 2 oz. Cu 0.06 thick single sided) with one die operating, 10s max.
280 EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) I pk = 7 A 240 200 160 120 80 40 0 25 50 75 100 125 150
10
100 ms 10 ms
10 ms
1
dc
0.1
RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT 1 10 100
0.01 0.1
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (C)
Figure 12. Maximum Rated Forward Biased Safe Operating Area
Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
1
D = 0.5 0.2 0.1 0.05 0.02 0.01
0.1
Normalized to qja at 10s.
Chip
0.0175 W 0.0710 W 0.2706 W 0.5776 W 0.7086 W
0.01 SINGLE PULSE 0.001 1.0E-05 1.0E-04 1.0E-03 1.0E-02
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient 1.0E+03
1.0E-01 t, TIME (s)
1.0E+00
1.0E+01
1.0E+02
Figure 14. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 15. Diode Reverse Recovery Waveform
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MMDF2P02E
PACKAGE DIMENSIONS
SOIC-8 NB CASE 751-07 ISSUE AH
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1 4
S
0.25 (0.010)
M
Y
M
-Y- G C -Z- H D 0.25 (0.010)
M SEATING PLANE
K
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2 7. DRAIN 1 8. DRAIN 1
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
E-FET and MiniMOS are trademarks of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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MMDF2P02E/D

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